 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| YTD428 IDSU DSU LSI for the ISDN Terminal Equipment INTRODUCTION YTD428 is a LSI which provides the ISDN subscriber interface (two-wire time compression multiplexing operation) and the NT side of the ISDN Basic Rate user-network interface function (digital four-wire time-division full-duplex operation). It is capable of providing the electric characteristics conforming to TTC Standard JT-I430 and JT-G961. YTD428 incorporates the circuit termination and line termination functions on a single chip allowing the user to easily configure a DSU (Digital Service Unit) that consumes small amount of power at a minimal cost. In addition, a TTL interface is provided at the T reference point (layer 1 level). This feature is especially effective when combined with YAMAHA's ISDN LSI for S/T reference point interface, YTD423 or YTD418. It allows considerable cost reduction on parts around the pulse transformer when constructing a device with a built-in DSU. The driver/receiver section of the T reference point interface can be separated from the DSU section and be used independently. The user can enable or disable this feature as necessary. YTD428 CATALOG CATALOG No.:4TD428A2 2001.1 Features s Circuit Termination Section s q Conforms to TTC Standard JT-I430 and JT-G961 Digital four-wire time-division full-duplex operation q Two-wire time compression multiplexing operation Transmission rate at U reference point: 320 kbit/s, at T reference point: 192 kbit/s q Frame assembling and disassembling function q q q q State transition control Loopback function T reference point timing control (switch between short passive bus / extended passive bus, point-to-point) U reference point driver control q s Line Termination Section s q q Conforms to TTC Standard JT-G961 f equalizer Bridged tap equalizer s T Reference Point Interface Section q The T reference point driver / receiver section can be separated from DSU section, and use independently (TE mode). The user can enable or disable this feature as necessary. s Others q q +5 V single power supply 100 pin SQFP -2- BLOCK DIAGRAM Internal Block Diagram YTD428 U ref. pt. I/F section Variable Amplifier ADC Peak hold T ref. pt. I/F section CT/LT section CT block Interface switch section T ref. pt. driver T ref. pt. receiver LT block U ref. pt. driver control TTL I/F S/T ref. pt. LSI YTD418 or YTD423 CT : Circuit Termination LT : Line Termination U ref. pt. side -3- T ref. pt. side DSU Configuration Example YTD428 incorporates the circuit termination, line termination, T reference point interface and U reference point interface functions on a single chip allowing the user to easily configure a DSU that consumes small amount of power at a minimal cost. The user can select from the two types of configurations. One is the general configuration in which a transformer is used at the T reference point interface. The other is a configuration in which a TTL interface is used to directly connect to the T reference point LSI. s Configuration example of a general DSU Various functions are incorporated on a single chip allowing the user to create a low power-consuming product at a low cost. Layer 3 info. Bch data T ref. pt. included driver/receiver for S/T ref. pt. TA / TB L2 U ref. pt. driver Call control circuit -4- U ref. pt. side YM7405 or YTD410 for S/T ref. pt. RA / RB DSU YTD428 L1 s Configuration example of a device with a built-in DSU that uses a TTL interface at the T ref. pt. When using YTD428 with YAMAHA'S S/T reference point interface LSI to create a device with a built-in DSU, they can be connected directly through the TTL interface. This results in a reduction of pulse transformer parts. T ref. pt. side (to terminal) YTD428 RA / RB T ref. pt. I/F TA / TB I/F switch CT and LT U ref. pt. I/F DSU section L2 U ref. pt. driver Call control circuit TTL I/F (No transformer is requied) YTD418 or YTD423 Layer 3 information (Bch data) s Example of using T reference point driver / receiver section independently By setting the Interface switch, the drive / receiver of the T reference point interface section can be separated from the circuit termination (CT) and line termination (LT) section and be used independently. The user can enable or disable this feature as necessary. T ref. pt. side (DSU) YTD428 RA / RB T ref. pt. I/F TA / TB I/F switch CT and LT U ref. pt. I/F DSU section L2 U ref. pt. driver Call control circuit TTL I/F (No transformer is required) YTD418 or YTD423 Layer 3 information (Bch data) U ref. pt. side L1 U ref. pt. side L1 -5- Pin Assignments DVDD TEST3 TEST2 TEST1 TEST0 LPSEL LOCAL DVSS RESET POWMON REV NTSEL MULTI TSMPAUT TSMPSEL ODSEL RDP TDP CLK192K DVDD LTD HTD LRD HRD DVSS TEST4 TEST5 TEST6 TEST7 LOOP2A LPSW TEST8 DVSS CLK1536 DVDD CLK4K CLK256K CLK200 CLK400 DVSS EXID TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 DVDD TEST16 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 -6- TEST17 TEST18 TEST19 TEST20 TEST21 TEST22 CLKSEL DVSS UDM0 UDM1 UDP0 UDP1 DVDD TEST23 TEST24 TEST25 TEST26 TEST27 TEST28 DVSS AVSS1 VRB VRT AVDD1 ATEI 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 YTD428-S 100pin SQFP 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AVSS2 RX LO2 AVDD2 LO1 CX1 AVDD2 LI2 CX2 LICT LI1 AVSS2 AVSS1 SXA SGBP SGB RXS AVDD1 SGA RUC RXU2 SGR AVSS1 RXU1 ATEO ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Storage Temperature Symbol VDD VI Tstg Min. VSS - 0.3 VSS - 0.3 - 50 Max VSS + 7.0 VDD + 0.3 + 125 Units V V C Recommended Operating Conditions Parameter Supply Voltage Operating Temperature Symbol VDD Top Range 5.0 V 5 % -20 ~ +70 C -7- DC Characteristics (DVDD = AVDD = 5 .0V, DVSS = AVSS = 0.0 V, Operating Temperature: Top = 25 C) Parameter Analog Output Allowable Load Impedance Analog Receive Buffer Input Impedance Analog Signal Reference Voltage ADC Note 1 Note 2 Note 3 Note 4 Note 5 Symbol ZO Zi1 VSG VRT VRB Condition Note 1 Note 2 Note 3 Note 4 Note 5 Min. 30 10 2.45 0.7AVDD - 0.1 0.3AVDD - 0.1 Typ. Max. Units k M 2.50 0.7AVDD 0.3AVDD 2.55 0.7AVDD + 0.1 0.3AVDD + 0.1 V V V Self-Bias VRT Self-Bias VRB With respect to SGR, SXA pins. With respect to RXU1 and RXU2 pins. Set SGR pin to open. With respect to VRT pin. With respect to VRB pin. (DVDD = AVDD = 5.0 V, Top = -20 ~ 70 C) Parameter High Level Input Voltage (TTL) Symbol VIH VIH VIL VIL VIH VIL VOH Condition (Note 1) (Note 2) (Note 1) (Note 2) (Note 3) (Note 3) (Note 4) (Note 5) (Note 4) (Note 5) (Note 6) Min. 2.2 3.0 Typ. Max. Units V V Low level Input Voltage (TTL) High Level Input Voltage (CMOS) Low Level Input Voltage (COMS) High Level Output Voltage (TTL) 0.8 0.8 3.5 1.0 DVDD - 1.0 DVDD - 1.0 DVSS + 0.4 DVSS + 0.4 DVSS + 0.4 -10 -10 10 10 36 V V V V V V V V V A A mA Low Level Output Voltage (TTL) Low Level Output Voltage (Open-D) Leak Current Idle Condition Leak Current Power Supply Current Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 VOL VOL IL ILZ IDD (Note 7) With respect to the digital pins other than RESET, POWMON, CLK1536 and TEST23 ~ 28 pins With respect to RESET, POWMON pins With respect to CLK1536, TEST23 ~ 28 pins With respect to the pin other than HRD, LRD pins Test condition: Output Current "H" level (IOH) = -0.2 mA, Output Current "L" level (IOL) = 1.2 mA With respect to HRD, LRD pins (when ODSEL = "H"), With respect to HRD, LRD pins (when ODSEL = "L"), With using T ref. pt. analog interface Test condition: IOH = -0.2 mA, IOL = 1.2 mA Test condition: IOL = 1.2 mA -8- AC Characteristics s T Reference Point Receive Characteristic (NT mode) (VDD = 5.0 V, Top = -20 ~ 70 C, Load Capacity: CL = 50 pF) Parameter Transmit Pulse Width Receive Pulse Width Rise Time Fall Time Phase Diffierence between Tx and Rx signals Phase Difference between Rx signals Symbol tTPW tRPW tPR tPF tTRD tTRD tPH tPH Note 1 Note 2 Note 1, Note 3 Note 2, Note 3 10.0 10.0 Condition Min. 5.00 Typ. 5.208 5.208 260 30 14.0 42.0 4.0 2.0 Max. 5.40 Units s s ns ns s s s s Note 1 Note 2 Note 3 With respect to using the Fixed timing With respect to using the Adaptive timing This value shows the difference between two terminals which are connected with bus system. t TPW HRD 2.0 V F 0.8 V t TPW 2.0 V LRD L Transmit data slot 0.8 V t RPW HTD t RPW t TRD F t FD Receive data slot 2.4 V 0.4 V 2.4 V LTD t PR L 0.4 V t PF Figure 1 Timing At T Ref. Pt. Interface -9- s T Reference Point Receive Characteristic (TE mode) (VDD = 5.0 V, Top = -20 ~ 70 C, CL = 50 pF) Parameter Symbol tRDR Delay Time tRDL tRDH tRDF Rise Time Fall Time Note 1 Note 2 tRR tRF Note 1 Note 2 Condition Min. Typ. Max. 700 200 700 700 30 30 Units ns ns ns ns ns ns With respect to HRD, LRD pins (ODSEL = "H") With respect to HRD, LRD pins Note 3 Figure 2 shows the timing when RDP = "H". When RDP = "L", the output signal polarity from HRD and LRD pins are inverted. Receive signal (I) (LI1 - LI2) t RDR t RR HRD (O) t RDH t RR LRD (O) t RDF t RF t RDL t RF 0V 2.0V 0.8 V 2.0 V 0.8 V Figure 2 Receive Timing - 10 - s T Reference Point Transmit Characteristic (TE mode) (VDD = 5.0 V, Top = -20 ~ 70 C, CL = 50 pF) Parameter HTD, LTD Pulse Period HTD, LTD Pulse Gap HTD, LTD Rise Time HTD, LTD Fall Time Symbol tSW tGAP tSR tSF tSRL Transmit Signal Delay Time tSRH tSFH tSFL Zero Cross Delay Time Note 1 Note 2 Condition Min. 4.95 0 Typ. Max. 5.45 260 260 30 Units s ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 0 490 0 165 490 490 1010 165 685 1010 tSDZ Measuring with RL voltage drop as shown in Figure 4. Figure 3 shows the timing when TDP = "H". When TDP = "L", the output signal polarity from HRD and LRD pins are inverted. t SW HTD (I) t SR LTD (I) t SRH t SRL Transmit signal (O) (LOI - LO2) t SFL t SFH t SR t SRH t SRL t SF t SDZ t SFL t SFH 1.35 V 0.15 V -0.15 V -1.35 V 2.4 V 0.4 V t SF t SW t GAP 2.4 V 0.4 V Figure 3 Transmit Timing - 11 - 100 HTD LO1 RO YTD428 LTD LO2 RL 200 Transmit signal Figure 4 Transmit Block Test Circuit s Driver, Receiver I/O Impedance Parameters Receiver Input Impedance Driver Ouput Impedance Driver Ouput Impedance Note 1 Note 2 When no pulse is output. When pulse is output. Symbol ZLI ZLO1 ZLO0 Condition LI1 - LI2 LO1 - LO2 (Note1) LO1 - LO2 (Note2) Min. 50 50 Typ. Max. Units k k 15 - 12 - PIN DESCRIPTIONS - 13 - IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. Yamaha assumes no liability for incidental , consequential, or special damages or injury that may result from misapplication or improper use or operation of the Products. 4. Yamaha makes no warranty or representation that the Products are subject to intellectual property license from Yamaha or any third party, and Yamaha makes no warranty excludes any liability to the Customer or any third party arising from or related to the Products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. Examples of use described herein are merely to indicate the characteristics and performance of Yamaha products. Yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. Yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, fitness for a particular use and title. The specifications of this product are subject to improvement changes without prior notice. AGENCY Address inquiries to: Semiconductor Sales & Marketing Department Head Office 203, Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192 Tel. 81-539-62-4918 Fax. 81-539-62-5054 Tokyo Office 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. 81-3-5488-5431 Fax. 81-3-5488-5088 Osaka Office Namba Tsujimoto Nissei Bldg, 4F 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. 81-6-6633-3690 Fax. 81-6-6633-3691 All rights reserved 2001 |
Price & Availability of YTD428
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |